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Home  -  News  -  CIF Plasma Cleaner Empowers Self‑Cleaning Van‑der‑Waals Lamination Technology for Two‑Dimensional Materials | Joint Research Team from Hunan University Publishes Achievements in *Science Bulletin*!

CIF Plasma Cleaner Empowers Self‑Cleaning Van‑der‑Waals Lamination Technology for Two‑Dimensional Materials | Joint Research Team from Hunan University Publishes Achievements in *Science Bulletin*!

Time:2026-08-05      Click Count:15

A joint research team led by Associate Professor Chang Liu of Hunan University, together with researchers from the Shanghai Institute of Technical Physics (CAS) and Fudan University, has published a key breakthrough in the top Chinese academic journal Science Bulletin. The team developed the Elastic-Bevel-Stamp-assisted Thermal Lamination (EBTL) technology, solving classic industrial challenges of interfacial contamination, bubbles and wrinkles in 2D material stacking.
In the fabrication of the Elastic Bevel Stamp (EBS) for this study, the CIF CPC-F Plus plasma cleaner was applied for critical plasma activation and bonding pretreatment. This key process helps the research achieve an ultra-high interfacial cleanliness yield of over 95%, offering solid technical support for wafer-scale 2D material stacking and 3D integrated device development.
Atomically thin 2D materials can be stacked to construct functional van der Waals heterostructures for next-generation electronic devices. However, traditional lamination easily traps air, moisture and other impurities between material layers, causing defects that undermine device performance.
The newly proposed EBTL technology realizes self-cleaning van der Waals lamination. With an ultra-flat van der Waals adhesive layer and 150°C in-situ heating, the elastic bevel stamp performs uniform soft lamination to squeeze out interlayer impurities and remove surface adsorbed molecules. After optimizing stamp structural parameters, the team achieved high-efficiency, damage-free lamination on large-area 2D materials.
The EBTL technology delivers a stacking interfacial yield of over 95%, greatly improving the quality of 2D stacked structures and electronic device performance. The research also successfully demonstrated a fully van der Waals-laminated 2D transistor array, verifying the practical value of this innovative process.
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