CIF Spin Coaters Empower Client's Breakthrough: High-Speed, Low-Power Integrated Sensing-Storage-Computing System Published in Nano Letters

Time：2026-03-16 Click Count：12

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The prestigious international academic journal Nano Letters, a leading nanotechnology publication under the American Chemical Society (ACS), has recently published online a groundbreaking study on Crystal Axis-aligned Oxygen-intercalated Transistors (COT).This innovative research successfully integrates polarization sensing, photocurrent storage, and optoelectronic logic functions within a single device. This breakthrough provides an entirely new technical pathway for developing next-generation, high-speed, and low-power integrated sensing-storage-computing systems.

In this significant scientific endeavor, the research team selected the CIF Spin Coater SC1, which provided critical technical support for the preparation of experimental samples.

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In data-intensive applications such as smart sensing and autonomous driving, traditional systems rely on physically separated sensing, storage, and computing units. The cross-unit transmission of massive raw data results in persistently high latency, bandwidth bottlenecks, and power consumption. Although "two-in-one" architectures like near-sensor computing and in-memory computing have emerged, they often rely on heterogeneous integration technologies. Constrained by differences in material systems and device structures, achieving high-density compatible integration remains challenging. Therefore, developing devices with multiple functions embedded within a single physical unit has become a critical direction for breaking through traditional architectural bottlenecks.

Addressing the stringent process requirements for fabricating 2D material heterojunction devices, CIF Spin Coaters play an irreplaceable supporting role, ensuring the precise preparation of core device structures:

High-Precision Spin Coating for Structural Foundation: The system precisely controls the preparation of critical thin films, including the PdSe₂ contact layer, the ReS₂ channel layer, and the oxygen intercalation layer. It ensures uniform thickness and surface flatness, providing crucial process guarantees for atomic-level clean van der Waals interfaces and precise crystal axis-aligned stacking.
Stable Adaptability for Higher Yield: With excellent operational stability and tunable parameters, the equipment perfectly matches the preparation needs of 2D anisotropic materials. It reduces thin-film defects caused by process fluctuations and ensures the uniform and confined distribution of oxygen intercalation, laying a solid structural foundation for charge-trapping storage functions.
Compatible Integration for Industrialization: The equipment's processes are highly compatible with device integration workflows, aligning perfectly with the "multi-functional single device" architecture concept. This provides vital process feasibility support for transitioning the technology from the laboratory to scaled applications.

The research team successfully developed the COT (Crystal Axis-aligned Oxygen-intercalated Transistor). The core achievements include:

Exceptional Sensing Performance: By employing crystal axis-aligned stacking and van der Waals contacts between PdSe₂ and ReS₂, the device achieves a high polarization ratio of 8.4, a responsivity of 5.2×10⁷ A/W, and a specific detectivity of 7.8×10¹⁵ cm·Hz¹/²·W⁻¹, significantly outperforming traditional detectors.
Robust Storage Capabilities: The introduction of a 2.5 nm oxygen intercalation layer enables 33 linear storage states. The data retention time reaches 6×10⁴ seconds (extrapolated to 10 years), with stable environmental storage performance over 18 months.
Reconfigurable Optoelectronic Logic: Leveraging its high polarization sensitivity, the device utilizes polarized light as input to achieve wavelength-tunable, reconfigurable optoelectronic logic gates (AND logic at 914 nm and OR logic at 375 nm) with an ultra-low single-operation energy consumption of just 0.5-5 pJ.
Integrated Architecture: By integrating sensing, storage, and computing functions into one device, it provides a universal framework for the development of high-density integrated chips.
Figure 1. Structure and Characterization of the COT Device.
(a) Schematic illustration of the device fabrication process. Anisotropic PdSe₂ (semimetallic, bandgap ≈ 0.16 eV) is used as the source/drain electrodes, and anisotropic ReS₂ (semiconducting, bandgap ≈ 1.5 eV) serves as the channel. Oxygen molecules are pre-adsorbed on the ReS₂ surface and confined during the stacking process to form an interfacial O₂ layer. The PdSe₂−ReS₂ heterostructure is stacked along the aligned crystal axis (b-axis) to achieve a high polarization ratio; van der Waals contacts ensure high device performance; and the confined O₂ layer acts as a charge trapping layer to realize storage functionality.
(b) Cross-sectional atomic-resolution image of the PdSe₂/ReS₂/O₂ structure, revealing an O₂ interlayer with a thickness of approximately 2.5 nm.
(c) Magnified image of the PdSe₂−ReS₂ contact region, displaying a clean van der Waals interface. Elemental mapping confirms its composition and distribution.
(d) Optical image of the COT device. Due to their intrinsic anisotropic cleavage characteristics, both PdSe₂ and ReS₂ exhibit a strip-like morphology, and their stacking is precisely aligned along the b-axis.
(e) Schematic band diagrams of the COT device under different operating modes (sensing, storage, and logic).
Figure 2. Photoresponse and Memory Performance.
(a) Transfer characteristics ( $I_{d s} - V_{g s}$ ) of the COT device in the dark and under laser illumination at various power levels.
(b) Dependence of responsivity ( $R$ ) on gate voltage ( $V_{g s}$ ) and incident light power ( $P_{l i g h t}$ ), reaching a maximum value of $5 \times 1 0^{7}$ A/W.
(c) Left axis (bottom): Noise current measured at different gate voltages; Right axis (top): Calculated specific detectivity ( $D^{*}$ ), reaching up to $7.8 \times 1 0^{15}$ cm·Hz $^{1 / 2}$ ·W $^{- 1}$ .
(d) $I_{d s} - V_{g s}$ characteristics under linearly polarized light writing (LP-writing) and circularly polarized light erasing (GP-erasing) operations.
(e) Long-term retention characteristics of the photocurrent, including a complete power-off interval during the test. The inset shows the extrapolated retention time, indicating that approximately 60% of the photocurrent is retained after 10 years.
(f) Reversible cycling operations of linearly polarized light writing and circularly polarized light erasing.
(g) Multi-level memory characteristics. A total of 33 discrete memory states were obtained, with uniformly increasing readout currents. The inset shows the linear dynamic response (slope: 7.78 nC/state), confirming highly linear multi-level memory behavior.
(h) Long-term stability, demonstrating stable performance after 18 months of ambient storage.

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Figure 3. Crystal Axis Alignment and Polarization-Resolved Photoresponse.
Top panels: Schematics of the atomic structures and corresponding crystal axes of PdSe₂ (a), ReS₂ (b), and their aligned heterostructure (c).
Bottom panels: Angle-dependent Raman spectra of PdSe₂, ReS₂, and their aligned heterostructure. The Raman enhancement peaks observed in each individual monolayer also appear in the PdSe₂/ReS₂ structure, confirming the successful crystal axis alignment.
(d) Dependence of the extracted polarization ratio on the relative angle ( $α$ ) between the b-axes of the PdSe₂/ReS₂ heterojunction. The polarization ratio reaches its maximum only when the b-axes of both materials are parallel ( $α = 18 0^{\circ}$ ), highlighting the critical importance of crystal axis alignment.
(e) Readout current and memory characteristics of the device under illumination of a 660 nm laser with different polarization states.
(f) Variation of polarization-dependent photocurrent with the incident angle at different wavelengths (375, 532, 808, and 914 nm).
(g) 3D statistical map of the polarization-dependent photocurrent, demonstrating the broadband polarization-resolving capability of the COT device. V1−V4 represent the primary Raman peaks of PdSe₂; N1−N4 represent the primary Raman peaks of ReS₂.

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Figure 4. Reconfigurable Optoelectronic Logic Gates Based on the COT Device.
(a) Schematic of the single-device logic gate. Two polarized light beams with perpendicular (

⊥

, logic "0") and parallel (

∥

, logic "1") polarization directions serve as logic inputs (

p, q

), while the source-drain current (

S

) acts as the logic output.
(b) Schematic illustrating the working principle of the reconfigurable logic gate. Reconfigurable optoelectronic logic gates are achieved by utilizing polarized light of different wavelengths: 914 nm light realizes the AND function, while 375 nm light realizes the OR function. Here, an 80 V reset gate voltage pulse is applied before each logic operation.
(c) Demonstration of the AND logic operation under 914 nm illumination with perpendicular and parallel polarized light.

I_{d s}

is used as the logic output, and

V_{g s}

serves as the memory reset control terminal. A threshold current (

I_{t h}

) of 0.225 nA is adopted to distinguish between logic states "0" and "1".
(d) Demonstration of the OR logic operation under 375 nm illumination with perpendicular and parallel polarized light.

I_{d s}

is used as the logic output, with a threshold current (

I_{t h}

) of 1.25 μA distinguishing between logic states "0" and "1". An 80 V reset gate voltage pulse is applied before each logic operation. The wavelength-dependent reconfigurable logic gates originate from the wavelength-dependent photocurrent characteristics of the COT device.

The publication of the client team's research in this prestigious international journal marks a significant breakthrough in the field of multi-functional 2D material devices.

Looking ahead, CIF will continue to deeply engage in the R&D of experimental equipment, continuously adapting to the demands of cutting-edge technological advancements. Hand in hand with researchers, we will explore new possibilities in fields such as intelligent sensing and semiconductor integration, facilitating the translation of more innovative achievements and driving the technological upgrading of related industries.